Contents
Overview of TVT
problems with larger systems and only produces multi-coloured bitmap images.
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TVT harnesses the simulation configuration of the device netlist and plugs in a Verilog model of the target tester. In effect, TVT provides a virtual ATE environment for test engineers to bring up their ATE patterns early, while waiting for the physical device. Design and test engineers can get a head start on their different verification needs in a common simulation environment at their workstation.
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TVT provides engineers with an easy-to-use virtual desktop ATE which can perform parallel simulations of multiple time domain patterns, or independent scan pattern bursts.
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TVT delivers a proven method for uncovering design issues that could later compromise device characterization and approval. In practical applications, users have seen design, configuration, test program and device issues highlighted through the use of TVT.
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TVT simulates the translated vectors on the tester model, so test engineers can uncover errors that can be traced back to the designer's test bench or the translation process. For example, the test bench may include vectors the designer needed during design but failed to remove when sending the vectors to test.
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Using TVT, test engineers can also identify errors caused by device initialization differences between the test bench and the pattern generated by the ATE. TVT can help test teams discover if a device is attempting to run faster than the tester maximum and ultimately find an errors, such as an omitted clock divide stage. A design change can then be made before first silicon, eliminating a wafer spin, and saving substantial costs and delays later in the project.
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Test teams can also isolate and debug simple logic errors (a reversed sequence of bit values) after duplicating the same failure on TVT and applying simulation debug techniques.
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A common problem in tester setup typically occur when a device I/O pin is expected to be output but the tester's driver is still enabled. In some cases, an I/O contention error can be caused by a tester characteristic that is not documented. TVT can display waveforms which assist test engineers to locate problems and modify the vector set to prevent the contention from occurring.
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This type of problem involves bad vectors and their simulation or translation errors. By examining the TVT simulation output, test engineers can trace errors back to the first location where they occurred and compare the pattern with the pre-translated vector. If they match correctly, the information can be communicated to the design team so they can trace the error location, and identify and resolve the problem.
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